1. Field of the Invention
This invention relates generally to electrostatic discharge ("ESD") protection of integrated circuits and more specifically to the ESD protection for output drivers of mixed voltage integrated circuits.
2. Description of Related Art
A trend in integrated circuit technologies is to push the power supply voltage lower, such as from the standard 5 volt power supply to 3.3 volts and lower. Lower power supply voltages on integrated circuits lead to the design of input/output structures that are optimized for the lower supply voltages. However, many standard devices continue to rely on 5 volt power supplies. Thus, mixed voltage circuits are being implemented. In some cases, mixed voltage circuits are implemented which result in the application of 5 volt signals to integrated circuit input/output structures that are designed for lower voltages. Electrostatic discharge protection for the input/output structures must be designed to handle the mixed voltage condition.
In general, ESD protection for such mixed voltage interfaces has been based on MOSFET transistors in a cascode configuration. See Anderson, et al., "ESD Protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration," EOS/ESD SYMPOSIUM 1998-54, pp. 2A.1.1-2A.1.9. In this configuration, a first transistor has its drain connected to the pad and its gate connected to the power supply. The source of the first transistor is connected to the drain of the second transistor. The drain of the second transistor is connected to ground. In this way, when the pad is a higher voltage, such as five volts, the voltages across the terminals on the cascode connected transistors should not exceed 3.3 volts. Because the voltages which stress the cascode connected transistors are lower, the input/output structure is more reliable, and does not suffer significant hot-electron degradation.
In the Anderson, et al. paper, the use of a cascode configuration is taught for ESD protection. The ESD protection of Anderson, et al. is applied in parallel with circuits used to drive the output signals on the pads being protected. Both the transistors in the cascode configuration are laid out in one active region in order to reduce the trigger voltage for effective ESD protection. However, the driving circuit is laid out in a different active region in order to raise the ESD trigger voltage of the driver to a level larger than that of the protection circuit. While the scheme is suitable for ESD protection, it requires additional area on the integrated circuit for the multiple active regions.
U.S. Pat. No. 5,780,897 describes an alternative ESD protection clamp for mixed voltage I/O stages. In this alternative, cascode transistors are used for ESD protection clamps and output drivers are used for a single pad. However, the output drivers stage is placed in the region which receives the silicide process to improve the contacts made for signals being driven by the circuit. The ESD protection clamp is placed in a region which does not receive the silicide process because ESD performance of the clamp degrades severely in the silicide region. Thus, the problem of the larger layout area required by the Anderson et al. technology is not solved completely.
It is desirable to provide an ESD protected output driver for integrated circuits which is as small as possible. Further, it is desirable to provide such technology in a standard cell format which can be used for a wide variety of integrated circuits without substantial redesign.